Implementation of a Binary Neural Network on a Passive Array of Magnetic\n Tunnel Junctions

Abstract

The increasing scale of neural networks and their growing application space\nhave produced demand for more energy- and memory-efficient\nartificial-intelligence-specific hardware. Avenues to mitigate the main issue,\nthe von Neumann bottleneck, include in-memory and near-memory architectures, as\nwell as algorithmic approaches. Here we leverage the low-power and the\ninherently binary operation of magnetic tunnel junctions (MTJs) to demonstrate\nneural network hardware inference based on passive arrays of MTJs. In general,\ntransferring a trained network model to hardware for inference is confronted by\ndegradation in performance due to device-to-device variations, write errors,\nparasitic resistance, and nonidealities in the substrate. To quantify the\neffect of these hardware realities, we benchmark 300 unique weight matrix\nsolutions of a 2-layer perceptron to classify the Wine dataset for both\nclassification accuracy and write fidelity. Despite device imperfections, we\nachieve software-equivalent accuracy of up to 95.3 % with proper tuning of\nnetwork parameters in 15 x 15 MTJ arrays having a range of device sizes. The\nsuccess of this tuning process shows that new metrics are needed to\ncharacterize the performance and quality of networks reproduced in mixed signal\nhardware.\n