A 39-GHz High Image-Rejection Up-Conversion Mixer in 65-nm CMOS for 5G Communication

Abstract

This brief presents an up-conversion mixer with high image rejection ratio (IRR) for 5G mmWave communication. To achieve broadband IRR at mmWave frequency with high area efficiency, a current-mode second-order tunable notch filter embedded in a cascode radio frequency (RF) buffer is proposed to realize tracking of the pole and zero frequencies with the switch capacitor array. To address the local oscillator (LO) leakage and even-harmonic distortion, a double-balanced passive mixer is adopted. For better isolation and lower insertion loss, a capacitor-inductor-capacitor (C-L-C) <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${\pi }$ </tex-math></inline-formula> -type impedance network is introduced in the mmWave T/R switch, realizing the equivalent lumped quarter wave transmission line with high area efficiency. Fabricated in a 65-nm CMOS process, the up-conversion mixer consumes 48.6 mW from a 1.2-V supply. Within the 3-dB bandwidth from 36 to 40.6 GHz, the mixer has a peak conversion gain of 0 dB, and its measured output 1-dB gain compression point (OP1dB) varies from −3 to −1.8 dBm. With the proposed tunable notch filter, the up-conversion mixer achieves a measured IRR of more than 53 dBc from 36 to 40.6 GHz, with a peak value of 58 dBc at 38.2 GHz.