Improved Approximate Multipliers for Single-Precision Floating-Point Hardware Design

Abstract

This paper reveals that state-of-the-art integer approximate multipliers (AxMs) present dispensable blocks when specifically embedded within a floating-point (FP) architecture. This paper proposes and implements arithmetic simplifications that significantly improve four state-of-the-art AxMs for FP. The results for 32-bit FP (FP-32) show that our improved 24-bit integer AxMs (i.e., specific for FP) reduce area from about 4.2x up to 12.9x in four different AxMs when compared with the original 24-bit AxM generic integer multiplier. We also perform an AxC design space exploration (DSE) of FP-32 Least Mean Squares Adaptive Filters (LMS-AF) architectures employing the four improved AxM proposals. We present quality-energy and -area DSE trade-offs in an approximate FP-32 LMS-AF kernel, in terms of Pareto fronts, showing that we can still maintain a fully functional harmonics elimination. Pareto front total energy reduction ranges from 43.4 % (1.27x) to 70.3% (3.37x) w.r.t. the precise multiplier.