FPGA Implementation of Polyphase CIC Based Multistage Filter for Digital Receivers

Abstract

The main focus of this work is to propose suitable architectures for the decimation filter networks of digital receivers that use the reduced logic and are capable of receiving multiple communication standard signals. It also involves the design, simulation, and implementation of multi-stage multi-rate filter architectures with reduced Very Large Scale Integrated (VLSI) cost functions. In the first multi-stage architecture namely, the Multi-Standard Decimation Filter (MSDF) structure is proposed to cater to the need of reception of multi-standard receiver signals. The MSDF architecture is designed for GSM and WiMAX wireless communication specifications and its first stages are designed using Cascaded Integrator Comb (CIC) filters. In the second architecture, a modified MSDF structure is implemented using polynomial CIC filters to meet the multi-standard requirements. The third architecture concentrates on design parameters of polyphase CIC-based decimation filter and its implementation concepts. Spartan FPGA-based implementation results that the proposed polynomial CIC-based MSDF architecture provides 32.11% of area reduction when related with the multistage MSDF. The proposed polyphase CIC-based MSDF architecture provides 28.57% of dynamic power-saving and a 15.5% increase in speed when compared to polynomial-based MSDFC architecture. Thus, the proposed polyphase MSDF architecture provides low power and lesser delay solutions using a multistage decimation approach and it is best suited for multi-standard communication applications in digital receivers.