Optimum modulo schedules for minimum register requirements

Abstract

Modtdo schedulwsg is an eficient tech nzque for exploiting instruction level parallelism in a uaraety of ioopsl resulting in high performance code but increased register requirements. We present a combined approach that schedules the loop operations for the highest steady state throughput and minimum register requirements. Our method determines optimal register requirements for machines with jinite resources and for general dependence graphs. We compare the performance of this and other modulo schedulers for a benchmark of 6.29 loops from the Perfect Clubl SPEC-89, and the Livermore Fortran Kernels. Measurements demonstrate the potential of r-egister=sensittve modulo schedulers, wh~ch will be useful in evaluating the performance of register-sensitive modrslo scheduling heuristics.