A net-oriented method for realistic fault analysis

Abstract

In this paper, a net-oriented method to analyze realistic faults is presented. The key point of the method is to analyze the faults caused by a spot defect net by net. First the possible faults related to a net are extracted. Hence all faults in a layout are extracted by enumerating all nets on the layout. An approach to calculate the critical area with respect to each fault is also described. A formula is proposed to compute the fault weight theoretically instead of weighting a fault by counting the number of appearances of the fault. The proposed method has been implemented on a HP750 workstation. To demonstrate its practical performance, all layouts in iscas85 benchmarks as well as some other layouts ranging from 450 to 28,000 transistors have been analyzed. The results show that our method is much faster than other approaches published in literature.