Interlock Collapsing ALU For Increased Instruction-level Parallelism

Implementing precise interrupts in pipelined processors

James E. Smith, Andrew R. Pleszkun · IEEE Transactions on Computers · 1988 · 267 citations

Engineering, Computer Architecture, System-level Design +18

An Instruction Issuing Approach to Enhancing Performance in Multiple Functional Unit Processors

Acosta, Kjelstrup, Torng · IEEE Transactions on Computers · 1986 · 101 citations

Multiple Functional Units, Engineering, Instruction Issuing Approach +19

Limits of instruction-level parallelism

David W. Wall · ACM SIGOPS Operating Systems Review · 1991 · 89 citations

Instruction-level Parallelism Author, Engineering, Data Science +11

Interlock collapsing ALU's

S. Vassiliadis, James Phillips, B. Blaner · IEEE Transactions on Computers · 1993 · 57 citations

Engineering, Combinatorial Design, Computer Architecture +16

The WM computer architecture

Wm. A. Wulf · ACM SIGARCH Computer Architecture News · 1988 · 35 citations · Full text

Pa. Pittsburgh, Engineering, Alert Preferences +11