A 5-Channel Unipolar Fetal-ECG Readout IC for Patch-Based Fetal Monitoring

Abstract

This letter presents a 5-channel unipolar fetal electrocardiogram readout IC for monitoring the health of a fetus during pregnancy. Each readout channel includes an instrumentation amplifier, a programable gain amplifier and a successive approximation register ADC. A unipolar, common half branch reuse topology is used to achieve low noise, low power, low crosstalk between the channels high input impedance and high CMRR at the same time. Each channel achieves an input referred noise of 0.47 μVrms in 0.5 to 150 Hz, while consuming a power of 43.2 μW. The 5-channel system provides a CMRR of 98 dB and an interchannel crosstalk rejection of 95 dB. The chip is implemented in a standard 55-nm CMOS process and occupies an area of 4.0 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> . The whole chip, including five readout channels, leadoff detection, reference generation, autonomous data acquisition with on-chip sample storage and an interrupt-based serial peripheral host interface consumes a total power of 258 μW.