Architectural Support for Software-Defined Metadata Processing

TLDR

Optimized hardware can propagate and check software‑programmable metadata tags with low runtime overhead. The study generalizes hardware tagging to a generic architecture that supports software‑defined policies over arbitrary‑sized metadata, introducing optimizations that keep overhead low. The architecture employs microarchitectural optimizations and is applied to enforce four safety and security policies—spatial/temporal memory safety, taint tracking, control‑flow integrity, and code/data separation—along with a composite policy. The model matches hardware‑based efficiency while offering software flexibility, achieving modest runtime (≤10%) and power (≤10%) overhead, with increased energy (≤60%) and area (110%) on SPEC CPU2006 benchmarks.

Abstract

Optimized hardware for propagating and checking software-programmable metadata tags can achieve low runtime overhead. We generalize prior work on hardware tagging by considering a generic architecture that supports software-defined policies over metadata of arbitrary size and complexity; we introduce several novel microarchitectural optimizations that keep the overhead of this rich processing low. Our model thus achieves the efficiency of previous hardware-based approaches with the flexibility of the software-based ones. We demonstrate this by using it to enforce four diverse safety and security policies---spatial and temporal memory safety, taint tracking, control-flow integrity, and code and data separation---plus a composite policy that enforces all of them simultaneously. Experiments on SPEC CPU2006 benchmarks with a PUMP-enhanced RISC processor show modest impact on runtime (typically under 10%) and power ceiling (less than 10%), in return for some increase in energy usage (typically under 60%) and area for on-chip memory structures (110%).