A SiGe PA with dual dynamic bias control and memoryless digital predistortion for WCDMA handset applications

Abstract

The paper demonstrates a two-stage 1.95 GHz WCDMA handset RFIC power amplifier (PA) implemented in 1.8 mm/sup 2/ in a 250 nm SiGe BiCMOS process. With an integrated dual dynamic bias control of the collector current and the collector voltage in the output stage, the average power efficiency of the two-stage PA is improved by over a factor of two. An off-chip memoryless digital predistortion is also adopted to improve the linearity of the power amplifier, satisfying the 3GPP WCDMA adjacent channel power ratio (ACPR) specifications with 26 dBm average channel output power and a peak power-added efficiency of 27%.