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Deep Neural Networks have spurred a trend toward specialized hardware acceleration, yet most designs halt at initial implementation despite large performance gains. The paper introduces Minerva, an automated co‑design framework spanning algorithm, architecture, and circuit levels to optimize DNN accelerators. Minerva automates co‑design across algorithm, architecture, and circuit layers to tailor DNN accelerators. The approach achieves up to 8.1× average power reduction across five datasets without accuracy loss, enabling ultra‑low‑power DNN accelerators in the tens of milliwatts range.
The continued success of Deep Neural Networks (DNNs) in classification tasks has sparked a trend of accelerating their execution with specialized hardware. While published designs easily give an order of magnitude improvement over general-purpose hardware, few look beyond an initial implementation. This paper presents Minerva, a highly automated co-design approach across the algorithm, architecture, and circuit levels to optimize DNN hardware accelerators. Compared to an established fixed-point accelerator baseline, we show that fine-grained, heterogeneous datatype optimization reduces power by 1.5×; aggressive, inline predication and pruning of small activity values further reduces power by 2.0×; and active hardware fault detection coupled with domain-aware error mitigation eliminates an additional 2.7× through lowering SRAM voltages. Across five datasets, these optimizations provide a collective average of 8.1× power reduction over an accelerator baseline without compromising DNN model accuracy. Minerva enables highly accurate, ultra-low power DNN accelerators (in the range of tens of milliwatts), making it feasible to deploy DNNs in power-constrained IoT and mobile devices.