A sub-2W 39.8-to-44.6Gb/s transmitter and receiver chipset with SFI-5.2 interface in 40nm CMOS

Abstract

The introduction of 40Gb/s networks, spurred by 40Gb/s WDM growth, can alleviate bandwidth bottlenecks of Internet infrastructure while simultaneously reducing operating costs. Increasingly, standard CMOS technology is used to enable transceiver speeds [1-5] previously achievable only by using expensive bipolar technology. However, at 40Gb/s, limited channel bandwidth coupled with stringent receiver jitter tolerance requirements demands better solutions than exist currently.