Publication | Closed Access
A 400 MHz S/390 microprocessor
23
Citations
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References
2002
Year
Unknown Venue
Hardware SecuritySystem On ChipElectrical EngineeringEngineeringVlsi DesignIbm S/390 ArchitectureComputer EngineeringComputer ArchitectureSystems EngineeringMhz S/390 MicroprocessorProcessor ClockIbm Cmos5x TechnologyComputer ScienceParallel ComputingMicroelectronicsProcessor ArchitectureHardware ArchitectureMulti-channel Memory Architecture
A microprocessor implementing IBM S/390 architecture operates in a system at up to 400 MHz (2.5 ns). The microprocessor, initially in IBM CMOS5X technology, migrated to CMOS6S by shrinking the FET length dimensions but not shrinking the interconnect dimensions. The chip is 17.35/spl times/17.30 mm/sup 2/ with about 7.8M transistors. The power supply is 2.5 V and measured power dissipation at 300 MHz is 37 W. The microprocessor features two instruction units, two fixed point units, two floating point units, a buffer control element, and a register unit. It dispatches one instruction per cycle. A PLL provides a processor clock at 2/spl times/ the system bus frequency.
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