Publication | Closed Access
Global interconnect sizing and spacing with consideration of coupling capacitance
34
Citations
13
References
1997
Year
Unknown Venue
Multiple NetsElectrical EngineeringPhysical Design (Electronics)EngineeringAdvanced Packaging (Semiconductors)3D Ic ArchitectureComputer EngineeringComputer ArchitectureGlobal Interconnect SizingGiss SolutionsNetwork On ChipInterconnection NetworkInterconnection Network ArchitectureElectronic PackagingMicroelectronicsGlobal Wire SizingInterconnect (Integrated Circuits)Electromagnetic Compatibility
The paper presents an efficient approach to perform global interconnect sizing and spacing (GISS) for multiple nets to minimize interconnect delays with consideration of coupling capacitance, in addition to area and fringing capacitances. We introduce the formulation of symmetric and asymmetric wire sizing and spacing. We prove two important results on the symmetric and asymmetric effective fringing properties which lead to a very effective bound computation algorithm to compute the upper and lower bounds of the optimal wire sizing and spacing solution for all nets under consideration. Our experiments show that in most cases the upper and lower bounds meet quickly after a few iterations and we actually obtain the optimal solution. To our knowledge, this is the first in depth study of global wire sizing and spacing for multiple nets with consideration of coupling capacitance. Experimental results show that our GISS solutions lead to substantially better delay reduction than existing single net wire sizing solutions without consideration of coupling capacitance.
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