The sizing rules method for analog integrated circuit design

TLDR

The paper introduces the sizing rules method for analog CMOS circuit design, aiming to streamline design by providing a hierarchical library of transistor pair groups, a generic constraint list, and automated block recognition. The method builds a hierarchical library of transistor pair groups, derives a generic list of constraints to ensure block functionality and reliability, and automatically recognizes building blocks in circuit schematics. The sizing rules method efficiently captures technology‑specific design knowledge, reduces preparatory modeling effort, and has proven effective in industrial applications such as circuit sizing, design centering, response surface modeling, and analog placement, yielding robust, technically meaningful results.

Abstract

Presents the sizing rules method for analog CMOS circuit design that consists of: first, the development of a hierarchical library of transistor pair groups as basic building blocks for analog CMOS circuits; second, the derivation of a hierarchical generic list of constraints that must be satisfied to guarantee the function of each block and its reliability with respect to physical effects; and third, the development of an automatic recognition of building blocks in a circuit schematic. The sizing rules method efficiently captures design knowledge on the technology-specific level of transistor pair groups. This reduces the preparatory modeling effort for analog circuit synthesis. Results of industrial applications to circuit sizing, design centering, response surface modeling and analog placement show the significance of the sizing rules method. Sizing rules especially make sure that automatic circuit sizing and design centering lead to technically meaningful and robust results.