Configurable 3D‐integrated focal‐plane cellular sensor–processor array architecture

Abstract

Abstract Mixed‐signal cellular visual microprocessor architecture with digital processors is described. An Application Specific Integrated Circuit (ASIC) implementation is also demonstrated. The architecture is composed of a regular sensor readout circuit array, prepared for 3D face‐to‐face‐type integration, and one or several cascaded array of mainly identical (single instruction multiple data, SIMD) processing elements. The individual array elements were derived from the same general Hardware Description Language (HDL) description and could be of different sizes, aspect ratio, and computing resources. Copyright © 2008 John Wiley & Sons, Ltd.