A 1.5 W single-chip MPEG2 MP@ML encoder with low power motion estimation and clocking

TLDR

Pipeline‑parallel motion‑estimation designs for MPEG‑2 require high clock frequencies and generate large power dissipation, and clock‑distribution power depends on peak rather than average performance, leading to waste. The study aims to create a practical single‑chip MPEG‑2 encoder LSI by reducing power dissipation and chip size. This is achieved by employing adaptive search‑area motion estimation and demand clocking within the encoder. These techniques eliminate the wasteful peak‑performance clock‑distribution power, reducing overall power consumption.

Abstract

To produce practical single-chip MPEG2 encoder LSIs, it is important to reduce power dissipation and chip size. Low-efficiency pipeline-parallel processing designs for motion estimation (ME) require not only high clock frequency but also large power dissipation. Clock distribution is also a major factor in power dissipation. In conventional designs the power required for clock distribution depends not on the average performance but on the peak-performance required. This represents a waste of power. In response to this, adaptive search-area ME and demand clocking are used in a single-chip MPEG2 encoder LSI.