ACM SIGARCH Computer Architecture News · 2000 · 166 citations · 11 references
EngineeringComputer EngineeringComputer ScienceComputer ArchitectureMemorySystem-on-chip DesignData Locality OptimizationMemory HierarchyMemory Hierarchy DesignMemory Hierarchy OptimizationMemory ManagementMemory Subsystem DesignLocality Of ReferenceMemory Access LatencyMemory Access LocalityMemory Access SchedulingMemory BandwidthMemory Bandwidth OptimizationMemory Locality OptimizationMemory Ordering
Memory bandwidth and latency depend on how accesses interact with the 3‑D bank/row/column structure of modern DRAM, with an order‑of‑magnitude difference between intra‑row and inter‑row references, making efficient scheduling crucial for media processors that must maximize scarce bandwidth. The study introduces memory access scheduling, a technique that reorders memory references to exploit 3‑D locality. By reordering references to exploit locality within the 3‑D bank/row/column structure, the technique improves memory system performance. Applying conservative reordering yields a 40% bandwidth increase, while aggressive reordering boosts bandwidth by 93% on media benchmark traces.
The bandwidth and latency of a memory system are strongly dependent on the manner in which accesses interact with the “3-D” structure of banks, rows, and columns characteristic of contemporary DRAM chips. There is nearly an order of magnitude difference in bandwidth between successive references to different columns within a row and different rows within a bank. This paper introduces memory access scheduling, a technique that improves the performance of a memory system by reordering memory references to exploit locality within the 3-D memory structure. Conservative reordering, in which the first ready reference in a sequence is performed, improves bandwidth by 40% for traces from five media benchmarks. Aggressive reordering, in which operations are scheduled to optimize memory bandwidth, improves bandwidth by 93% for the same set of applications. Memory access scheduling is particularly important for media processors where it enables the processor to make the most efficient use of scarce memory bandwidth.
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David A. Patterson, Thomas E. Anderson, Neal Cardwell et al. · IEEE Micro · 1997 · 668 citations
Impulse: building a smarter memory controller
J. Carter, Wilson C. Hsieh, Leigh Stoller et al. · 1999 · 233 citations
Ashley Saulsbury, Fong Pong, Andreas Nowatzyk · 1996 · 193 citations