Predictions of CMOS compatible on-chip optical interconnect

TLDR

Interconnect is a primary bottleneck in integrated circuit design, and as CMOS scales, conventional copper interconnect increasingly fails to meet delay, power, bandwidth, and noise requirements, prompting consideration of on‑chip optical interconnect as a potential substitute. This paper predicts the performance of CMOS‑compatible optical devices using current state‑of‑the‑art optical technologies. The authors compare electrical and optical interconnects across various design criteria based on these predictions. They find that optical interconnect becomes advantageous over electrical interconnect when the critical dimension exceeds roughly one‑tenth of the chip edge length at the 22 nm technology node.

Abstract

Interconnect has become a primary bottleneck in integrated circuit design. As CMOS technology is scaled, it will become increasingly difficult for conventional copper interconnect to satisfy the design requirements of delay, power, bandwidth, and noise. On-chip optical interconnect has been considered as a potential substitute for electrical interconnect in the past two decades. In this paper, predictions of the performance of CMOS compatible optical devices are made based on current state-of-art optical technologies. Electrical and optical interconnects are compared for various design criteria based on these predictions. The critical dimensions beyond which optical interconnect becomes advantageous over electrical interconnect are shown to be approximately one tenth of the chip edge length at the 22 nm technology node.