Standby Bias Improvement of Read After Write Delay in Ferroelectric Field Effect Transistors

Abstract

Read after write has been a significant challenge in front-end ferroelectric field effect transistors (FEFETs) due to the read speed being fundamentally limited by the speed of neutralization of charged interfacial oxide states which are captured and screen the polarization of the ferroelectric. We investigate two approaches to bypassing the fundamental limitation to FEFET read-after-write speed by altering the temperature and bias condition during standby to change the rates of neutralization for trap states. We find that it is possible to improve the read after write speed to~ 400 ns by applying a standby bias of ±1.5 V which is an over 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">5</sup> improvement in the speed of the device. This speed improvement is accomplished by changing the fermi level of the device hence reducing the emission time and increasing the capture time of opposite trap type thus neutralization time constant of the interfacial trap states. This work suggests that the read after write speed is not a showstopper for FEFETs which can potentially be solved by engineering the write pulse.