Low-Power and Scalable Retention-Enhanced IGZO TFT eDRAM-Based Charge-Domain Computing

Abstract

This paper presents a power-efficient, scalable and robust approach to the design of eDRAM-based compute-in-memory (CiM) accelerator for artificial neural networks using the back-end-of-line (BEOL) compatible amorphous-Indium-Gallium-Zinc (a-IGZO) TFT technology. The highlights include: (i) IGZO TFTs with ultra-low leakage current, high on-state current of <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$157\mu \mathrm{A}/\mu \mathrm{m}$</tex> for 45nm devices, and excellent subthreshold swing as low as 71mV/dec and 105mV/dec for <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$5\mu\mathrm{m}$</tex> and 45nm devices, respectively; (ii) a novel 4T1C eDRAM differential CiM cell that tolerates <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$\sigma(V_{\text{TH}})=50\text{mV}$</tex> and <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$\sigma(C_{\mathrm{C}})/C_{\mathrm{C}}=2\%$</tex> for accurate 128-row 8-bit MAC operations, and achieves >50× longer retention time during computing than the prior TFT eDRAM cells; (iii) a charge-domain coupling-based CiM technique that enables low sensing complexity and high computing power efficiency by avoiding DC power and complex timing control. Experiment-calibrated benchmarking in VGG-8 network for CIFAR-10 image classification tasks shows 2092 TOPS/W power efficiency for the CiM core and 795 TOPS/W including peripherals, and outperforms prior TFT and CMOS-based CiM approaches in a range of event density.