A 0.8-V, 2.55-GHz, 2.62-mW Charge-Pump PLL With High Spectrum Purity

Abstract

This article presents a low supply voltage and low-power charge-pump phase-locked loop (CPPLL) with phase noise (PN) improvement and reference spur reduction techniques. The <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$V_{\mathrm {ref}}$ </tex-math></inline-formula> adaptive adjustment mechanism is analyzed in the class-C voltage-controlled oscillator (VCO) with dual-mixed loops, which eliminates the PN’s sensitivity to temperature and process. Moreover, based on resistance-based accurate current replication, the low-power and low-current mismatch charge-pump (CP) circuit structure is proposed to reduce the reference spur of the PLL. In addition, by using the dynamic current compensation scheme, the power consumption of the CP is greatly reduced. The proposed PLL is fabricated in a 0.18- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu \text{m}$ </tex-math></inline-formula> RF CMOS process with an area of 1.07 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\times $ </tex-math></inline-formula> 1.07 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> . The measurement results show that the proposed PLL achieves a 2.24–2.85-GHz frequency tuning range and a PN of −123.97 dBc/Hz at 1-MHz offset from a 2.55-GHz carrier. The measured reference spur is −89.4 dBc at 40-MHz offset frequency and the total power consumption is 2.62 mW at the 0.8-V power supply voltage.