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Crossbar based Processing in Memory Accelerator Architecture for Graph Convolutional Networks
21
Citations
32
References
2021
Year
Graph Representation LearningMachine LearningEngineeringComputer ArchitecturePim-gcn ArchitectureGraph ProcessingRepresentation LearningData ScienceMemory Accelerator ArchitectureComputing SystemsParallel ComputingGraph Convolutional NetworksGraph AlgorithmsComputer EngineeringGraph Data StructuresComputer ScienceDeep LearningHardware AccelerationGraph TheoryParallel ProgrammingGraph AnalysisGraph Neural NetworkGraph Data
Graph data structures are central to many applications such as social networks, citation networks, molecular interactions, and navigation systems. Graph Convolutional Networks (GCNs) are used to process and learn insights from the graph data for tasks such as link prediction, node classification, and learning node embeddings. The compute and memory access characteristics of GCNs differ, both from conventional graph analytics algorithms and from convolutional neural networks, rendering the existing accelerators for graph analytics as well as deep learning, inefficient. In this work, we propose PIM-GCN, a crossbar-based processing-in-memory (PIM) accelerator architecture for GCNs. PIM-GCN incorporates a node-stationary dataflow with support for both Compressed Sparse Row (CSR) and Compressed Sparse Column (CSC) graph data representations. We propose techniques for graph traversal in the compressed sparse domain, feature aggregation, and feature transformation operations in GCNs mapped to in-situ analog compute functions of crossbar memory, and present the trade-offs in performance, energy, and scalability aspects of the PIM-GCN architecture for CSR, and CSC graph data representations. PIM-GCN shows an average speedup of over <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$3-16\times$</tex> and an average energy reduction of <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$4-12\times$</tex> compared to the existing accelerator architectures.
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