A DC–28-GHz 7-Bit High-Accuracy Digital-Step Attenuator in 55-nm CMOS

Abstract

This letter presents an ultrawideband 7-bit digital-step attenuator (DSA). Capacitive compensation technique is utilized to improve the amplitude and phase accuracy and enable wideband operation. The attenuator is implemented in a 55-nm CMOS process and occupies 0.044-mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> core area. It demonstrates a 15.9-dB attenuation range with a 0.125-dB step size. The measured insertion loss (IL) is 2.7–6.6 dB at dc–28 GHz and the rms amplitude and phase errors of four measured chips are < 0.15 dB and <0.8°, respectively. The return loss is better than 12 dB for all the 128 attenuation states. To the best of our knowledge, this chip demonstrates the highest attenuation accuracy and minimum phase variation among silicon-based DSAs with a similar dynamic range.