Sub-5 nm Gate Length Monolayer MoTe₂ Transistors

Abstract

Since silicon-based field-effect transistors (FETs) are approaching their scaling limit, two-dimensional (2D) semiconductors have been proposed as alternative channel materials. Recently, air-stable 2D trilayer (TL) MoTe2 FETs with a 4 nm gate length have been fabricated experimentally. To explore the device performance limit of the monolayer MoTe2 FETs, we simulate the sub-5 nm gate length double-gate (DG) ML MoTe2 FETs by using the ab initio quantum transport method. We find that when taking negative capacitance technology and underlap into account, the performances of the 3 nm gate length p-type DG ML MoTe2 FETs can satisfy the International Technology Roadmap for Semiconductor 2013 requirements for both the high-performance and low-power applications in the 2028 horizon. Thus, ML MoTe2 as channel materials can scale Moore’s law down to 3 nm.