A Partially Static High Frequency 18T Hybrid Topological Flip-Flop Design for Low Power Application

Abstract

In this brief, an extremely low power true <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$1-\phi $ </tex-math></inline-formula> clocking flip-flop is proposed using eighteen transistors only. The flip-flop is a synchronous bistable element that stores single-bit information. To design this Master Slave (MS) type architecture, topological, logical, and adaptive coupling techniques are employed. The minimum number of transistors are maintained by using above techniques, which comprises of complementary pass transistor logic and static complementary MOS logic. It also offers low power, a low delay that speeds up the flip-flops, and low complexity by reducing the transistor count. The proposed circuit is implemented using Cadence Virtuoso and compared with the five other reported logic structures of flip-flops. The proposed hybrid logic architecture has showed the highest percentage, i.e., 49.73% improvement in terms of power as compared to LRFF. It also improved the delay and energy efficiency (EDP). The Monte Carlo simulation has been performed for C to Q Delay for 20K samples. By reducing the number of PMOS transistors, the total area of the proposed flip-flop reduces by a minimum of 9.49% in comparison to state of the art work. The proposed circuit can work properly within a frequency range upto 1 GHz. It is also compared with reported 18T TSPC flip-flop.