A 0.15mm² Energy-Efficient Single-Ended Capacitance-to-Digital Converter

Abstract

In this brief, we proposed a small area, high precision, and high energy efficiency single-ended capacitance-to-digital converter (CDC). The circuit incorporates a <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\Delta \Sigma $ </tex-math></inline-formula> CDC and a SAR CDC. The SAR CDC is a coarse CDC which determines the measurement range of capacitance, considering the area consumption, single-ended SAR CDC is adopted. To get a high resolution, inverter-based correlated-double-sampling (CDS) circuit is employed in the <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\Delta \Sigma $ </tex-math></inline-formula> modulation loop. The test chip is fabricated in a 180-nm CMOS process and the core occupies an area of 0.15mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> . The circuit achieves an rms resolution of 186aF at a 4pF input capacitor, the power consumption is <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$4.1~\mu \text{W}$ </tex-math></inline-formula> in SAR phase with a 100kHz sampling rate and <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$23.2~\mu \text{W}$ </tex-math></inline-formula> in <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\Delta \Sigma $ </tex-math></inline-formula> phase with a 400 kHz sampling rate.