Fast polar codes for terabits-per-second throughput communications

Abstract

Targeting high-throughput and low-power communications, we implement two successive cancellation (SC) decoders for polar codes. Converted to 16nm ASIC technology, the area efficiency and energy efficiency are 4Tbps/mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> and 0.63pJ/bit, respectively, for the unrolled decoder, and 561Gbps/mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> and 1.21pJ/bit, respectively, for the recursive decoder. To achieve such a high throughput, a novel code construction, coined as fast polar codes, is proposed and jointly optimized with a highly-parallel SC decoding architecture. First, we reuse existing modules to fast decode more outer code blocks, and then modify code construction to facilitate faster decoding for all outer code blocks up to a degree of parallelism of 16. Furthermore, parallel comparison circuits and bit quantization schemes are customized for hardware implementation. Collectively, they contribute to an 2.66× area efficiency improvement and 33% energy saving over the state of the art.