One stage gain boosted power driver at 184 GHz in 28 nm FD-SOI CMOS

Abstract

In order to improve amplifiers' power gain for a close to <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$f_{max}$</tex> operation, a methodology to size the embedding of any active two port is described and then applied to the design of a single-stage amplifier as a proof of concept. The 184 GHz measured 28 nm FD-SOI CMOS amplifier presents a power gain of 7.6 dB, a bandwidth of 20 GHz, a <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$P_{sat}$</tex> of −3.7 dBm and a peak PAE of 4.2% for a power consumption of 5.1 mW.