A Method of Partial Inductances to Evaluate and Optimize Switching Cells

Abstract

Advances in wide-bandgap devices have enabled increased switching frequencies in modern power converters. As a result, the parasitic inductance arising from switching cell layout has become critical to converter performance and operation. This inductance not only reduces slew rate, which degrades efficiency, but can also cause electromagnetic interference and destructive voltage overshoot. This paper presents a method for estimating the inductance of printed circuit board (PCB) commutation loops, targeted for rapid iteration by the power electronics designer. Based on partial inductances, the computationally efficient approach is amenable to fast parametric sweeps. The proposed technique is also platform-independent, such that it may be scripted into existing optimization tools. To validate the accuracy of the technique, a detailed quantitative comparison is performed with commercial simulation tools as well as experimental measurements on a number of hardware prototypes.