Test Scheduling and Test Time Reduction for SoC by Using Enhanced Firefly Algorithm

Abstract

System-on-Chip (SoC) is an integration of electronic components and billions of transistors. Defects due to the base material is caused during the manufacturing of components. To overcome these issues testing of chips is necessary but total cost increases because of increasing test time. The main issues to be considered during testing of SoC are the time taken for testing and accessibility of core. Effective test scheduling should be done to minimize testing time. In this paper, an effective test scheduling mechanism to minimize testing time is proposed. The test time reduction causes test cost reduction. The Enhanced Firefly algorithm is used in this paper to minimize test time. Enhanced Firefly algorithm gives a better result than Ant colony and Firefly algorithms in terms of test time reduction thereby reduction test cost takes place.