Inkjet‐Printed Ternary Oxide Dielectric and Doped Interface Layer for Metal‐Oxide Thin‐Film Transistors with Low Voltage Operation

Abstract

Abstract Additive solution process patterning, such as inkjet printing, is desirable for high‐throughput roll‐to‐roll and sheet fabrication environments of electronics manufacturing because it can help to reduce cost by conserving active materials and circumventing multistep processing. This paper reports inkjet printing of Y x Al 2− x O 3 gate dielectric, In 2 O 3 semiconductor, and a polyethyleneimine‐doped In 2 O 3 interfacial charge injection layer to achieve a thin‐film transistor (TFT) mobility (μ sat ) of ≈1 cm 2 V −1 s −1 at a low 3 V operating voltage. When the dielectric material is annealed at 350 °C, plasma treatment induces low‐frequency capacitance instability, leading to overestimation of mobility. On the contrary, films annealed at 500 °C show stable capacitance from 1 MHz down to 0.1 Hz. This result highlights the importance of low‐frequency capacitance characterization of solution‐processed dielectrics, especially if plasma treatment is applied before subsequent processing steps. This study progresses metal‐oxide TFT fabrication toward fully inkjet‐printed thin‐film electronics.