iWarp: an integrated solution to high-speed parallel computing

TLDR

iWarp is a high‑speed computing architecture for signal, image, and scientific workloads, covering systems from special‑purpose systolic arrays to general‑purpose distributed memory computers. This paper presents the iWarp architecture and its support for multiple communication models and system configurations. An iWarp system is built from a single‑chip processor component (the iWarp cell) that, with added memory, delivers 20 MFLOPS of computation and 320 MBytes/s, 100‑150 ns latency communication, and can scale to 1,024 cells. The iWarp component’s strong compute and communication make it a versatile building block that supports both fine‑grain parallel and coarse‑grain distributed models, and an 8×8 torus demo delivers over 1.2 GF.

Abstract

iWarp is a system architecture for high speed signal, image and scientific computing. The heart of an iWarp system is the iWarp component: a single chip processor that requires only the addition of memory chips to form a complete system building block, called the iWarp cell. Each iWarp component contains both a powerful computation engine (20 MFLOPS) and a high throughput (320 MBytes/sec), low latency (100-150 ns) communication engine for interfacing with other iWarp cells. Because of its strong computation and communication capabilities, the iWarp component is a versatile building block for various high performance parallel systems. These systems range from special purpose systolic arrays to general purpose distributed memory computers. They are able to support both fine-grain parallel and coarse-grain distributed computation models simultaneously in the same system. An iWarp system can include a large number of cells; the initial iWarp demonstration system consists of an 8x8 torus of iWarp cells, delivering more than 1.2 GFLOPS. It can be expanded to include up to 1,024 cells. This paper describes the iWarp architecture and how it supports various communication models and system configurations.