A zero-skew clock routing scheme for VLSI circuits

Abstract

A clock routing scheme that guarantees a zero-skew routing result is proposed. It is shown that the time complexity for the algorithm can be reduced to O(n/sup 2/ log n) by using the modified Voronoi diagram to structure the algorithm. L-shaped pairing and H-flipping operations are introduced to further reduce the clock wire length. Extensions are made to the algorithm for use in building-block layout and zero skew is also achieved. Significant reduction in total clock wire lengths is observed.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>