A 45nm 8-core enterprise Xeon® processor

Abstract

The next-generation enterprise Xeon <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">reg</sup> server processor consists of eight dual- threaded 64b Nehalem cores and a shared L3 cache. The system interface includes two on-chip memory controllers and supports multiple system topologies. This design has 2.3B transistors and is implemented in 45 nm CMOS using metal-gate high- <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">K</sub> dielectric transistors and nine Cu interconnect layers. The thermal design power is 130 W.