A wideband 10-bit, 20 Msps pipelined ADC using current-mode signals

Abstract

A 10-b BiCMOS analog-to-digital converter (ADC) is used to demonstrate a current-mode pipeline system that overcomes some of the limitations of high-speed multiple-flash architectures. Although multistage ADCs are efficient in both die area and power, a track-and-hold amplifier (T/H) is required to prevent the input from changing while a conversion is taking place. If the ADC is pipelined (operating on more than one sample at a time), a T/H is required between each pipeline stage. Additionally, for resolution greater than about 8 b interstage amplification is required. The settling behavior of the T/Hs and amplifiers dominates the performance of these ADCs. To address these problems, a differential current-mode architecture incorporates current-mode T/Hs, obviating the need for interstage amplifiers. The prototype chip achieves 10 b of resolution at 20 Msample/s with an 80-MHz input bandwidth and dissipates 1 W.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>