2008 · 69 citations · 14 references
ComputingComputer EngineeringComputer ScienceField-programmable Gate ArraysLow-power DesignParallel ComputingComputer Graphics HardwareGraphics Processing Unit ArchitectureGraphics Processing Unit ComputingGraphics Processing UnitsHardware AccelerationKernel ProgrammingCuda ProgrammingGpu ArchitectureGpu Programming ModelsKernel OptimizationMemory BandwidthMemory UtilizationShared MemoryShared Memory Optimization
Most GPU performance “hypes” have focused around tightly-coupled applications with small memory bandwidth requirements e.g., N-body, but GPUs are also commodity vector machines sporting substantial memory bandwidth; however, effective programming methodologies thereof have been poorly studied. Our new 3-D FFT kernel, written in NVIDIA CUDA, achieves nearly 80 GFLOPS on a top-end GPU, being more than three times faster than any existing FFT implementations on GPUs including CUFFT. Careful programming techniques are employed to fully exploit modern GPU hardware characteristics while overcoming their limitations, including on-chip shared memory utilization, optimizing the number of threads and registers through appropriate localization, and avoiding low-speed stride memory accesses. Our kernel applied to real applications achieves orders of magnitude boost in power&cost vs. performance metrics. The off-card bandwidth limitation is still an issue, which could be alleviated somewhat with application kernels confinement within the card, while ideal solution being facilitation of faster GPU interfaces.
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Ian Buck, Daniel Reiter Horn, Jeremy Sugerman et al. · ACM Transactions on Graphics · 2004 · 1.2K citations
David Tarditi, Sidd Puri, Jose Oglesby · 2006 · 297 citations
Fast matrix multiplies using graphics hardware
E. Scott Larsen, David McAllister · 2001 · 216 citations
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