Publication | Closed Access
IMPACT: IMPrecise adders for low-power approximate computing
369
Citations
14
References
2011
Year
Unknown Venue
EngineeringVlsi DesignComputer ArchitecturePortable Multimedia DevicesComputational ComplexityImprecise AddersHardware SecurityHigh-performance ArchitectureApproximate ComputingLogic Complexity ReductionParallel ComputingApproximation TheoryElectrical EngineeringComputer EngineeringComputer ScienceMicroelectronicsVoltage ScalingHardware AccelerationVlsi ArchitectureParallel ProgrammingDigital Circuit Design
Low‑power is critical for portable multimedia devices, and because human perception tolerates errors, prior work has leveraged voltage over‑scaling and algorithmic techniques to mitigate inaccuracies. This work proposes reducing logic complexity as an alternative to voltage over‑scaling and designs video and image compression architectures that employ the resulting approximate arithmetic units. The authors create transistor‑level imprecise full adders that reduce switched capacitance and critical path delay, enabling the construction of approximate multi‑bit adders and voltage scaling. Simulations show up to 60 % power and 37 % area savings with negligible loss in output quality compared to existing implementations.
Low-power is an imperative requirement for portable multimedia devices employing various signal processing algorithms and architectures. In most multimedia applications, the final output is interpreted by human senses, which are not perfect. This fact obviates the need to produce exactly correct numerical outputs. Previous research in this context exploits error-resiliency primarily through voltage over-scaling, utilizing algorithmic and architectural techniques to mitigate the resulting errors. In this paper, we propose logic complexity reduction as an alternative approach to take advantage of the relaxation of numerical accuracy. We demonstrate this concept by proposing various imprecise or approximate Full Adder (FA) cells with reduced complexity at the transistor level, and utilize them to design approximate multi-bit adders. In addition to the inherent reduction in switched capacitance, our techniques result in significantly shorter critical paths, enabling voltage scaling. We design architectures for video and image compression algorithms using the proposed approximate arithmetic units, and evaluate them to demonstrate the efficacy of our approach. Post-layout simulations indicate power savings of up to 60% and area savings of up to 37% with an insignificant loss in output quality, when compared to existing implementations.
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