Sub-ns Polarization Switching in 25nm FE FinFET toward Post CPU and Spatial-Energetic Mapping of Traps for Enhanced Endurance

Abstract

In this work, we report sub-ns polarization switching in highly scaled 25 nm ferroelectric (FE) FinFET with Hf <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0.5</sub> Zr <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0.5</sub> O <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> (HZO) ferroelectric (FE)/SiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> dielectric (DE) gate stack for high performance CPU application for the first time. Observed limited endurance was attributed to the increase of trap density in the stack, which was quantitatively analyzed upon program/erase cycles by various methods including newly adopted low-frequency noise (LFN) characteristics for resolving spatial and energetic distribution of traps. In particular, we identified three different types of traps at FE/DE interface (D <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">it_2</sub> ) and SiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> /Si channel interface (D <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">it_1</sub> ) as well as in the bulk oxide (N <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ot</sub> ) of the HZO/SiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> gate stack of FE FinFETs. In addition, with the developed trap analysis, we investigated radiation-induced degradation of HZO/SiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> gate stack for application under harsh environments. Highly scaled and high performance FE FinFETs with enhanced endurance would provide a viable solution for future platform of low-power computing.