Sub-5 nm Monolayer MoS₂ Transistors toward Low-Power Devices

Abstract

Inspired by the recent achievements of the two-dimensional (2D) sub-5 nm MoS2 field effect transistors (FETs), we use the ab initio quantum-transport methods to simulate the transport properties of the sub-5 nm gate-length monolayer (ML) MoS2 MOSFETs. We find that the ML MoS2 double-gated MOSFETs (DGFETs) with the 1, 3, and 5 nm gate length fail to meet the on-state current requirements in the International Technology Roadmap for Semiconductors (ITRS) for high-performance (HP) devices. However, both the ML MoS2 n- and p-DGFETs with 5 nm gate length can address the requirements in the ITRS for low-power (LP) applications in terms of on-state current, effective delay time, and power-delay products (PDPs). After the introduction of the negative capacitance dielectric layer, the ML MoS2 p-DGFETs can satisfy the LP application requirements of ITRS until the gate length scales down to 3 nm. Hence, ML MoS2 remains a potential channel candidate for LP applications in the sub-5 nm scale.