10.5 A 12b 600MS/s Pipelined SAR and 2x-Interleaved Incremental Delta-Sigma ADC with Source-Follower-Based Residue-Transfer Scheme in 7nm FinFET

Abstract

Recently, pipelined ADCs are frequently adopted as sub-ADCs in multi-channel timeinterleaved ADCs because a pipelined manner can reduce the number of interleaved channels by maximizing single-channel ADC operating speed. To reduce power consumption of residue amplifier, previous works [2], [4], [5] have explored power efficient residue amplifier architecture, such as dynamic amplifiers (DAs), open-loop amplifiers (OAs) and ring amplifiers (RAs). However, inter-stage gain error of power-efficient DAs, OAs, and RAs needs power-consuming gain calibration to compensate process, power supply, and temperature (PVT) variations.