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Symmetric-Mapping LUT-Based Method and Architecture for Computing X<sup>Y</sup>-Like Functions
21
Citations
17
References
2021
Year
Numerical AnalysisTheory Of ComputingReal Data TypeNumerical ComputationEngineeringReference CircuitAlgebraic ComplexityComputer EngineeringMathematical FoundationsComputational ComplexityTime ComplexityComputer ScienceSymmetric-mapping Lookup TableParallel ComputingPower ConsumptionSymbolic ComputationSymmetric-mapping Lut-based Method
We propose a new method and hardware architecture to compute the functions expressed as XY (X and Y are arbitrary floating-point numbers), which can support arbitrary Nth root, exponential and power operations. Because of the complexity of direct computation, we usually convert it to logarithm, multiplication, and antilogarithm operations. Traditional approaches suffer from long latency, large area and high power consumption. To solve this problem, we propose a symmetric-mapping lookup table (SM-LUT) to be capable of computing log <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> x (x ∈ [1, 2]) and 2 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">x</sup> (x ∈ [0, 1]) simultaneously. It lays the foundation for computing XY. To further improve hardware performance of our architecture, we propose a multi-region address searcher to speed up the calculation of SM-LUT. In addition, we use an optimized Vedic multiplier to shorten the critical path and improve the efficiency of multiplication, which is included in computing XY. Under the TSMC 40nm CMOS technology, we design and synthesize a reference circuit to compute XY with a maximum relative error of 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-3</sup> . The report shows that the reference circuit achieves the area of 14338.50 μm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> and the power consumption of 4.59 mW at the frequency of 1 GHz. In comparison with the state-of-the-art work under the same input range and similar precision, it saves 78.57% area and 80.42% power consumption for N√R computation and 82.89% area and 81.89% power consumption for RN computation averagely. On top of that, our architecture reduces the computation latency by 62.77% averagely and has one more order of magnitude of energy efficiency than others.
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