2020 · 10 citations · 4 references
EngineeringElectrical EngineeringAnalog ElectronicsLow-power DesignMicroelectronicsCmos Circuit DesignLow-noise Circuit DesignNoiseNoise In Analog CircuitsNoise In Semiconductor DevicesNoise ReductionLow-dropout Regulator DesignLow-dropout RegulatorsLow-pass FilteringLow-pass FiltersLow-power Cmos DesignLow-voltage Cmos DesignPower Supply RejectionPower Supply Rejection Ratio
This paper presents a low-dropout regulator (LDO) with the capability to provide a stable 0.9 V supply voltage for fluctuation-sensitive circuits such as the voltage-controller oscillator in a frequency synthesizer. The LDO uses a low noise architecture that separates two feed-back loops with a low-pass filter with a extremely low 3-dB frequency of 8.15 Hz. The circuit is designed in a 28-nm technology, operating with a 1.8 V external voltage and able to supply maximum current of 25 mA. Analysis and implementation for optimizing power supply rejection ratio (PSRR) of the circuit are also addressed in this paper.
4
Yizhe Hu, Teerachot Siriburanon, Robert Bogdan Staszewski · IEEE Journal of Solid-State Circuits · 2018 · 163 citations · Full text