Investigation of Temperature and Source/Drain Overlap Impact on Negative Capacitance Silicon Nanotube FET (NC Si NTFET) with Sub-60mV/decade Switching

Abstract

In this paper, the impact of temperature and source/drain overlap on DC characteristics and analog/RF performance of the negative capacitance silicon nanotube FET (NC Si NTFET) have been presented. The performance of the device is examined by coupling the 3D TCAD numerical simulation with 1D Landau-Khalatnikov (LK) equation. The effect of negative capacitance has been investigated for different source/drain overlap lengths (L <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ov</sub> ) at 300 K and 380 K. The optimal values of source/drain overlap lengths and effective ferroelectric thickness (t <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">f</sub> ) have been found to attain significant improvement in device performance in terms of drain current (I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">d</sub> ), subthreshold swing (SS), gate capacitance (C <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">g</sub> ), and cut-off frequency (f <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">t</sub> ). It is reported that a minimum SS of 30.7 mV/decade, and maximum f <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">t</sub> of 2.35 THz are achieved for NC Si NTFET at 300 K for an operating frequency of 1 GHz. It is observed that the core (inner gate) radius (t <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">c</sub> ) can be used to increase the minimum SS and I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ON</sub> to delay the hysteresis and to achieve a better drive current.