Hardware Implementation of Neuromorphic Computing Using Large‐Scale Memristor Crossbar Arrays

TLDR

Neuromorphic computing promises to overcome energy and speed limits of von Neumann architectures, and memristor crossbar arrays—capable of vector‑matrix multiplication and tunable conductance—are a leading technology for building large‑scale artificial neural networks that emulate the brain’s hierarchical structure. The report aims to guide the hardware implementation of neuromorphic computing systems by recommending device, circuit, and algorithm optimizations for building large‑scale, high‑density memristor crossbar arrays that enable complex artificial neural networks. The authors analyze the strict device performance and array parameter requirements for hardware ANNs and discuss strategies to meet these challenges. Recent experimental demonstrations of neuromorphic computing systems using memristor crossbar arrays are highlighted.

Abstract

Brain‐inspired neuromorphic computing is a new paradigm that holds great potential to overcome the intrinsic energy and speed issues of traditional von Neumann based computing architecture. With the ability to perform vector‐matrix multiplications and flexible tunable conductance, the memristor crossbar array (CBA) structure is one of the most promising candidates to realize neural cognitive systems. The boom in the development of memristive synapses and neurons has propelled the developments of artificial neural networks (ANNs) to emulate the highly hierarchically organized network of human brain in the past decade. To achieve this, realizing large scale, high‐density memristive CBAs is a prerequisite to constructing complex ANNs. Herein, the stringent requirements in device performance and array parameters for hardware ANNs are analyzed, and the efforts in addressing the associated challenges are discussed. Recent progress on the experimental demonstration of neuromorphic computing systems (NCSs) is presented. Recommendations for further performance optimization at the device, circuit, and algorithm levels are proposed. This Report serves as a guide for the hardware implementation of NCS based on large‐scale CBAs.