Parasitic Inductance Modeling and Reduction for Wire-Bonded Half-Bridge SiC Multichip Power Modules

Abstract

This article first developed an inductance model that includes the parasitic mutual inductance between parallel current path segments for SiC multichip power modules. Based on the developed model, the SiC multichip module's transient response was analyzed, important parasitic inductances were identified. The layout was improved based on the transient analysis. The improved package layout can reduce the parasitic inductance without increasing the fabrication difficulty. Experiments were conducted to validate the reduction of parasitic inductances. The parasitic ringing and the crosstalk effect were significantly reduced with the proposed technique. The thermal performance was also improved with the proposed layout.