A 4-Element 7.5-9 GHz Phased Array Receiver with 8 Simultaneously Reconfigurable Beams in 65 nm CMOS Technology

Abstract

This paper presents a 4-element 7.5-9 GHz phased array receiver with 1-8 concurrent beams in a 65-nm CMOS technology. All the elements are fully-connected to each output beam using 32 phase shifters and 8 active combiners. The current-starving gm-based phase shifter with 6-bit phase resolution achieves <; 2° RMS phase error and <; 0.3 dB RMS gain error. The receiver demonstrates 20 dB gain, 3.6 dB noise figure (NF) and -19 dBm input 1-dB gain compression point (IP1dB) in 7.5-9 GHz band for each element. The chip occupies 5.42 × 3.62 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> area excluding pads and consumes 860 mW, equivalent to 27 mW per element per beam. To our knowledge, the receiver achieves the maximum number of simultaneously reconfigurable beams with the lowest power consumption per element per beam in RF phase shifting and combining receiver chips.