Area/Power-Efficient True-Single-Phase-Clock D-Flipflops with Improved Metastability

Abstract

This paper investigates the metastability of true-singlephase-clock (TSPC) D flipflops (DFFs). The cause of the metastability of the DFFs, both positive edge-triggered (PET) and negative edge-triggered (NET), is investigated and the theoretical expressions of the setup time and hold time of the DFFs are obtained. The asymmetry of setup time and hold time is investigated. It is shown TSPC DFFs suffer from a large hold time but enjoy zero setup time. The hold time of NET-DFFs is significantly larger as compared with that of PET-DFFs. An area-power efficient shunt capacitor technique capable of sharply reducing hold time while marginally increasing setup time is proposed and its effectiveness is verified using simulation results.