2020 · 20 citations · 0 references
EngineeringElectrical EngineeringAnalog ElectronicsLow-power DesignSystem-on-chip DesignAnalog Integrated CircuitsCmos Circuit DesignDigital Signal ProcessingLow-noise Circuit DesignLow-power Digital Circuit DesignMixed-signal Integrated Circuit DesignAnalog-digital ConversionAnalog-to-digital ConversionAnalog-to-digital ConvertersCmos Analog Circuit DesignCmos Analog Integrated CircuitsNoise Power Spectral DensityPower Spectral DensityTwo-stage Amplifier Design
This paper presents a SAR ADC with reduced front-end sampling kT/C noise. This is achieved by using an active sampling circuit with a specially designed 2-stage amplifier that decouples the tight relationship between the sampling noise power spectral density (PSD) and BW. A 12-bit 12-MS/s prototype ADC in 40nm CMOS achieves the sampling noise power reduction by 3.5 times. It permits the use of a small sampling capacitor of only 132 fF. This relaxes the requirement on the ADC input driver and reference buffer, which can lead to significant savings in power, area, and complexity on the system level.