Sub-5-nm Monolayer Silicane Transistor: A First-Principles Quantum Transport Simulation

Abstract

As one of the thinnest forms of semiconducting silicon, monolayer (ML) silicane has not only excellent gate electrostatics and carrier transport ability, but also compatibility with well-established silicon-based technology. We explore the device performance limits of sub-5-nm ML silicane metal-oxide-semiconductor field-effect transistors (MOSFETs) by applying ab initio quantum transport simulations. The on-state current, effective delay time, and power-delay product of the optimized n-type and p-type ML silicane MOSFETs can well or nearly meet the high-performance device requirements of the International Technology Roadmap for Semiconductors (ITRS) at a gate length of 5 nm. Those of the optimized n-type ML silicane MOSFETs at a gate length of 3 nm and the p-type ML silicane MOSFETs at a gate length of 5 nm can meet the low-power-device demands of the ITRS. Thus, ML silicane as channel materials can scale the Moore's law down to 5 nm.